High Bandwidth Memory (HBM) is a high-performance RAM interface for 3D-stacked dynamic random access memories (DRAMs), intended for applications such as high-performance graphics accelerators and network devices (see, e.g., “High Bandwidth Memory (HBM) DRAM (JESD235),” JEDEC, October 2013). HBM achieves higher bandwidth while using less power in a substantially smaller form factor than DDR4 or GDDR5 by stacking up to eight DRAM dies. The HBM memory bus is also very wide in comparison to other DRAM memories such as DDR4 or GDDR5. For example, an HBM stack of four DRAM dies has two 128-bit channels per die for a total of eight channels and a width of 1024 bits in total, with each channel interface operating at DDR data rates. A chip with four such stacks would therefore have a memory bus with a width of 4096 bits. In comparison, the bus width of GDDR memories is 32 bits, with 16 channels for a graphics card with a 512-bit memory interface. The second generation of high bandwidth memory, HBM 2, specifies up to 8 dies per staple and doubles throughput to 1 TB/s. In summary, the HBM DRAM uses a wide-interface architecture to achieve high-speed, low-power operation.
Although much higher in performance, HBM includes many of the same features of DDR, including the need for read and write data path training. The purpose of read and write data path training is to identify the delay at which the read and write DQS rising edges align with the beginning and end transitions of the associated DQ data eye. By identifying these delays, the system can calculate the midpoint between the delays, then align the read/write DQS to the accurate centers of the read/write DQ data eye.
There are many conventional approaches to performing read and write data path training for DDR memories. See, e.g., Yong-Cheol Bae, Joon-Young Park et al., “A 1.2V 30 nm 1.6 Gb/s/pin 4 Gb LPDDR3 SDRAM with Input Skew Calibration and Enhanced Control Scheme,” ISSCC Dig. Tech. Papers, pp. 44-46, February 2012; Munkyo Seo, Sopan Joshi, Ian A. Young, “A Blind Calibration Technique to Correct Memory Errors in Amplifier-sharing Pipelined ADCs,” IEEE International Symposium on Circuit and Systems, 2007; Devendra Rai, Lothar Thiele, “A Calibration Based Thermal Modeling Technique for Complex Multicore Systems,” Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, pp. 1138-1143, March 2015; Ho Joon Lee, Yong-Bin Kim, “A Process Tolerant Semi-Self Impedance Calibration Method for LPDDR4 Memory Controller,” IEEE 58th International Midwest Symposium on Circuit and Systems (MWSCAS), pp. 1-4, August 2015; U.S. Pat. No. 6,316,980 to Pete D. Vogt et al. titled “Calibrating Data Strobe Signal Using Adjustable Delays with Feedback”; U.S. Pat. No. 7,558,132 to Michael Joseph Carneval et al. titled “Implementing Calibration of DQS Sampling During Synchronous DRAM READs”; U.S. Pat. No. 6,442,102 to John Michail Borkenhagen et al, titled “Method and Apparatus for Implementing High Speed DDR SDRAM Read Interface with Reduced ACLV effects”; U.S. Patent Publ. No. 2007/0233942 to Hsiang-I Huang et al. titled “Method for Calibration of Memory Devices, and Apparatus Thereof”; and U.S. Pat. No. 7,594,750 to Seung-Hoon Lee et al. titled “Method for Outputting Internal Temperature Data in Semiconductor Memory Device and Circuit of Outputting Internal Temperature Date Thereby.”
However, challenges can arise when attempting to implement these conventional DDR training schemes in HBMs. None of these references recognize or address these challenges.